发明名称 METHOD AND DEVICE FOR ARRANGING LSI
摘要 PROBLEM TO BE SOLVED: To enable a designer to perform rearranging work with high efficiency by clearly displaying information about a critical path in a state the arrangement position of a block is changed/corrected. SOLUTION: An LSI arranging method has a step S1 for reading circuit information as read information, a step S2 for displaying the arrangement information of the block on the basis of the read information, a step S3 for selecting one unarranged or arranged block, a step S4 for temporarily and provisionally arranging the selected block at a desired arrangement place, a step S5 for performing a simple delay calculation to calculate a wiring delay value, a step S6 for comparing the delay value obtained in the step S5 with a delay constraint value and recognizing wiring in which the delay value is larger as a critical path to display the wiring, a step S7 for deciding whether a block position is proper on the basis of critical path information, a step S8 for making the a block arrangement position a determined position, and a step S9 for deciding whether all blocks have been arranged and finishing the processing in the case no unarranged block exists.
申请公布号 JP2003030264(A) 申请公布日期 2003.01.31
申请号 JP20010211681 申请日期 2001.07.12
申请人 NEC MICROSYSTEMS LTD 发明人 KURATA MINORU;OKABE HIDEYUKI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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