| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory, in which suitable compatibility of high speed when it is operated and reduction of power consumption can be performed. SOLUTION: A pulse, generating a word line activation signal, is generated, based on a clock CLK in pulse generating sections 30, 40. The pulse signal, generated by the pulse generating section 40, is delayed by a pulse generated by a pulse generating section 30 by delay circuits 43, 44. In a selection circuit 60, the word-line activation signal is generated, based on an inputted read- command signal RE and a write-command signal WE. That is, a word line activation signal is generated, based on a pulse generated by the generating section 30 at the time of read operation, and based on a pulse generated by the pulse generating section 40, when write operation is carried out. |
