发明名称 METHOD FOR PLANARIZING DEPOSITED FILM
摘要 PROBLEM TO BE SOLVED: To reduce dishing which occurs, when overpolishing of CMP is terminated. SOLUTION: A wiring groove 12 is formed in an interlayer insulating film 11 on a semiconductor substrate 10 and a barrier metal layer 13 is formed on the surface of the interlayer insulating film 11, including the inner face of the wiring groove 12. A seed layer of copper 14 is formed on the barrier metal layer 13, and the seed layer 14 is made to grow by electroplating method, and a copper film 15 is deposited. The first step of CMP is performed on the copper film 15 and a planarized copper film 15A is obtained. The second step of CMP is performed on the planarized copper film 15A and an embedded wiring 15B is formed. A part, existing on the outer side of the wiring groove 12 in the barrier metal layer 13, is removed. The thickness of the copper film 15 is set to 1.6 to 2.0 times the depth of the wiring groove 12.
申请公布号 JP2003031577(A) 申请公布日期 2003.01.31
申请号 JP20010216446 申请日期 2001.07.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YOSHIDA HIDEAKI
分类号 H01L21/3205;H01L21/304;H01L21/306;H01L21/321;H01L21/768;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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