| 摘要 |
PROBLEM TO BE SOLVED: To reduce the power consumption of a digital still camera. SOLUTION: A CCD timing generating circuit for controlling an imaging device 13 in the digital still camera receives a high-speed clock pulse CLK 1. Low speed clock pulses CLK2, CLK3 and CLK4 are given to an AE/AF circuit 16, a signal processing circuit 17 and a medium controller 19. Since they are operated at a low speed, the power consumption can be reduced. |
