| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that the long time is required till input and output signals of a data slice circuit are stabilized and the PLL is locked when a reflection signal having the long passing time is omitted (at the defect passing time), since the variation of a DC voltage inputted to the data slice circuit is very large when the reflection signal is omitted (at the defect passing time), in the process of high speed playback of the low reflectance disk, and then the sound interruption of an output of audio signal occurs. SOLUTION: The unit is constituted in such a manner that a bypass filter means 47a for making only the high frequency component of a electrical signal pass through is arranged on a pre-stage of a data slice means 41 generating a modulation signal by binarizing a voltage signal, and a frequency changeover means 48 is provided for changing over a frequency of the bypass filter means 47a in accordance with a playback speed so as to changeover a signal frequency band inputted to the data slice means 41 in accordance with the playback speed.
|
