| 摘要 |
PROBLEM TO BE SOLVED: To suppress a change in a leading and a trailing of an output signal OUT to be at low speed so as to realize low power consumption and low noise while satisfying the DC characteristic. SOLUTION: For example, when a level at a point IN rises from 'L' to 'H', nodes N12, N13 go to 'L' and a PMOS 18 is conductive and an NMOS 19 is nonconductive. In this case, since a position OUT is at 'L' an output of a NAND 14 goes to 'H', an NMOS 16 is conductive and the node N12 is pulled up. Thus, the drive capability of the PMOS 18 gets smaller, and the OUT slowly goes to 'H'. When the level of the OUT is higher than a threshold voltage of the NAND 14, the output of the NAND 14 goes to 'L' and the NMOS 16 is nonconductive. Thus, the voltage of the node N12 reaches an off state resulting in bringing the drive capability of the PMOS 18 to an increased state so that the OUT rapidly goes up to 'H'.
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