| 摘要 |
PROBLEM TO BE SOLVED: To provide a CPU unit capable of making the changing timing of an operation condition such as an output pulse frequency shorter than one scan. SOLUTION: An ASIC in the CPU unit of a PLC is provided with a condition setting register 21 for temporarily storing the operation condition of an output pulse, a buffer 22 for storing the several sets of operation conditions stored in the condition setting register, a frequency-division ratio comparing register 23 and a number of output pulse counter 24 for storing the several sets of operation conditions stored in the buffer successively by each set, and a comparator 25 for comparing the counter value of the frequency-division ratio counter 26 with the set value set by the frequency-division ratio comparing register, and for outputting a pulse as set by the set value. Thus, the several sets of operation conditions are stored in a batch by one time scan so that the operation conditions can be changed in the middle of the next scan.
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