发明名称 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
摘要 One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
申请公布号 US2003021139(A1) 申请公布日期 2003.01.30
申请号 US20020185645 申请日期 2002.06.28
申请人 NAKAMURA HIROSHI;IMAMIYA KENICHI;TAKEUCHI KEN 发明人 NAKAMURA HIROSHI;IMAMIYA KENICHI;TAKEUCHI KEN
分类号 G11C7/10;G11C7/20;G11C16/20;(IPC1-7):G11C29/00;G11C5/06;G11C5/00;G11C8/00 主分类号 G11C7/10
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