| 摘要 |
A method for manufacturing a semiconductor device that maintains good embedding property of plug metal, and expands the short margin of upper wiring layers to be connected to plugs, may include enlarging an end region 18 of a hole 12, such that embedding of a barrier metal 13 and a plug metal 14 in the hole 12 that is given a high aspect ratio is facilitated. Next, a planarization step is conducted against deposited surfaces of the plug metal 14 by a chemical mechanical polishing (CMP) process. In this step, a part of the interlayer dielectric layer 11 is removed together with an unnecessary portion of the plug metal 14 to a level where the end region (having a diameter d2) that is greater than a practical diameter d1 of the hole 12 disappears. Then, an upper wiring layer 15 is patterned, using a lithography technique, on the planarized interlayer dielectric layer 11 having an exposed portion of the plug metal 14 that has the practical diameter of the hole.
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