Jitter reduction in clock signal, defines two operational states outputting either clock signal or combination of PLL signal and clock signal

摘要

In a first operating state, the output signal (32) is the clock signal (20). In a second, different operating state, the output signal is formed by the PLL (phase-locked loop) signal (28) of the phase control loop (10, 12, 14) and the clock signal (20). An Independent claim is included for corresponding equipment.