发明名称 |
Transfer network for addition of two bit groups such that circuit performance is enhanced and adding speed improved by use of a redundant logic circuit solely comprising NAND gates and inverters |
摘要 |
Method for generating a transfer signal (cy) from a transfer network (2) that is for adding two bit groups together (A, B) in an adder circuit, whereby the transfer network is implemented as a static hardware circuit. The circuit is based on a redundant logic circuit comprised solely of NAND gates (AI) and inverters (I). A further transfer path does not have inverters.
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申请公布号 |
DE10225862(A1) |
申请公布日期 |
2003.01.30 |
申请号 |
DE20021025862 |
申请日期 |
2002.06.11 |
申请人 |
IBM DEUTSCHLAND GMBH |
发明人 |
HALLER, WILHELM E.;SAUTTER, ROLF;WENDEL, DIETER;WETTER, HOLGER |
分类号 |
G06F9/30;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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地址 |
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