| 摘要 |
PURPOSE: To realize a DRAM where the influence of noise between bit lines which influence is exerted on memory cells is reduced, and the cell area is made 4F¬2. CONSTITUTION: First word lines WL1 and second word lines WL2, which are constituted of different layers, are arranged in parallel with each other in a row direction at the same pitch. The first word lines WL1 and the second word lines WL2 are arranged alternately having intervals which are one-half of the above pitch in the horizontal distance. Thereby memory cells MC are arranged on all intersections between the first word lines WL1 and one sides of bit line pairs and all intersections between the second word lines WL2 and the other sides of the bit line pairs. An MISFET for selecting a memory cell is made into a vertical structure, and a bit line positioned above a substrate, on which a channel region is formed, is shielded with a conducting film a part of which constitutes a gate electrode.
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