| 摘要 |
PURPOSE: A device and method for controlling power-down voltage is provided, which is capable of performing deep power down(DPD) entrance and exit with minimum current variation and preventing erroneous triggering of circuits when DRAM operates during DPD entrance or exit. CONSTITUTION: A plurality of input buffers(51,52,53,54,55) receive external input signals and output received signals to a DPD detect and controller(150). A plurality of internal power voltage generators(210,220,230,240) are supplied with reference voltages and various bias voltages such as a plate voltage, an internal array power voltage, a substrate bias voltage, an internal peripheral voltage, and a boost voltage. The DPD detect and controller(150) generates a DPD command signal(PDPDE) for turning off the input buffers(51,52,53,54,55) and the internal power voltage generators(210,220,230,240) when detecting pre-assigned combination of signals for signaling DPD enter and exit modes from the input buffers(51,52,53,54,55). An auxiliary input buffer(50) receives an external power-down command signal, and an auto pulse generator(300) generates a pulse(AP) when detecting a DPD exit command from the auxiliary input buffer(50).
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