发明名称 Volume rendering integrated circuit
摘要 A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.
申请公布号 US6512517(B1) 申请公布日期 2003.01.28
申请号 US19990315742 申请日期 1999.05.20
申请人 TERARECON, INC. 发明人 KNITTEL JAMES M.;BURGESS STEPHEN R.;CORRELL KENNETH W.;HARDENBERGH JAN C.;KAPPLER CHRISTOPHER J.;LAUER HUGH C.;MASON STEPHEN F.;OHKAMI TAKAHIDE;PEET WILLIAM R.;PFISTER HANSPETER;SCHULTZ BEVERLY J.;WILKINSON JAY C.
分类号 G06F15/16;G06F15/80;G06T1/20;G06T15/00;G06T15/08;G06T17/00;(IPC1-7):G06T17/00 主分类号 G06F15/16
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