| 摘要 |
The present invention relates to a via parasitics testing and extracting method for Gigabit multi-layered PCB boards. The method of the present invention is a unique test and extraction process that utilizes a TDR measurement and processes the output data therefrom externally. The testing aspect involves obtaining a TDR module waveform and obtaining a text file with output data, whereas the extraction aspect involves analysis of the data in the text file. This method can be used directly to ascertain a Gigabit via structure without the limitations that are imposed by the conventional methods discussed above, and has been theoretically proven to be highly accurate and much faster than any of the existing methods. The method of the present invention has the potential to be included as a built-in testing feature in high-speed TDR meters, and may also be used in order to design an optimized via.
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