| 摘要 |
First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit is provided for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information. With respect to data to be outputted first of the first and second data, output timing of the data to be outputted later is delayed, data to be outputted first is made to correspond to the first output register, data to be outputted later is made to correspond to the second output register, and the transfer rate of the second signal transmission path corresponding to the first output register is set higher than that of the second signal transmission path corresponding to the second output register.
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