Nonvolatile semiconductor memory device having a hierarchial bit line structure

摘要

A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in a matrix, wherein bit lines have hierarchical structures and comprise at least a main bit line 1 and a sub-bit line 2, and a plurality of sub-bit line selection transistors 4 provided between the main bit line 1 and sub-bit line 2 which transistor 4 are respectively selectively activated depending on given row address lines, wherein a voltage applied to each gate electrode of the sub-bit line selection transistor 4 which is selected and activated when data is erased from or written on each memory cell is rendered the same as that applied to each gate electrode of the sub-bit line selection transistor 4 which becomes non-activated when not selected.