发明名称 |
Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter |
摘要 |
The invention provides an apparatus, and related method, for receiving and synchronizing parallel data transmitted over multiple serial data channels. The synchronization technique uses a channel lock FIFO buffer on each received serial data channel. The FIFO buffers are configured to tolerate a significant amount of jitter between channels and clock tree delay within the synchronization apparatus.
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申请公布号 |
US6512804(B1) |
申请公布日期 |
2003.01.28 |
申请号 |
US19990288000 |
申请日期 |
1999.04.07 |
申请人 |
APPLIED MICRO CIRCUITS CORPORATION |
发明人 |
JOHNSON DAVID T.;ROBALINO STEVEN G. |
分类号 |
H04J3/06;H04L25/14;H04Q11/04;(IPC1-7):H04L25/36;H04L25/40;H04L7/00 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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