发明名称 Technique for efficient logic power gating with data retention in integrated circuit devices
摘要 A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.
申请公布号 US6512394(B1) 申请公布日期 2003.01.28
申请号 US20020098872 申请日期 2002.03.14
申请人 UNITED MEMORIES, INC.;SONY CORPORATION 发明人 PARRIS MICHAEL C.
分类号 H01L21/8238;G05F3/24;H01L27/092;H03K19/00;H03K19/003;H03K19/0948;(IPC1-7):H03K17/16;G05F3/02 主分类号 H01L21/8238
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