发明名称 HIERARCHY LAYOUT DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROGRAM FOR MAKING COMPUTER EXECUTE THE METHOD
摘要 PROBLEM TO BE SOLVED: To connect low-order hierarchy functional blocks without specially providing a wiring area. SOLUTION: In a core area 11, a plurality of the low-order hierarchy functional blocks 31-34 are arranged at a narrow interval within the arranging area of a high-order hierarchy functional block 21. The arrangement of cells 41 and inter-cell wiring are performed in the low-order hierarchy functional blocks 31-34, and input/output terminals 41a used for the inter-cell connection are set so as to serve also as the signal connection terminals of the low-order hierarchy functional blocks. The low-order hierarchy functional blocks are connected by connecting the input/output terminals 41a using signal connection wiring 51, and the signal connection wiring 51 is constituted of a wiring layer through the high-order hierarchy functional block 21 and a via. The wiring layer and the via constituting the signal connection wiring 51 are different from the wiring layer and the via used for connecting the cells within the low- order hierarchy functional block.
申请公布号 JP2003023082(A) 申请公布日期 2003.01.24
申请号 JP20010209851 申请日期 2001.07.10
申请人 MITSUBISHI ELECTRIC CORP 发明人 IKEDA NOBUYUKI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/82 主分类号 G06F17/50
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