发明名称 SYNCHRONIZATION CLOCK GENERATING CIRCUIT, AND SYNCHRONIZATION CLOCK GENERATING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a synchronization clock generating circuit and a synchronization clock generating device, having a small scale circuit configuration that copes with a clock signal over a wide range, and simultaneously realize synchronism with high accuracy. SOLUTION: This invention provides the synchronization clock generating device that comprises a plurality of stages of the synchronization clock generating circuits, each provided with a delay circuit 110 that outputs a delay clock, a delay detection circuit 120 that detects the delay timing of a delayed clock, a storage device 130 that stores the output of the delay detection circuit 120 at reception of a synchronization pulse, a selection circuit 150 that selects a delay clock most closely synchronized with the synchronizing pulse E, a delay period clock generating circuit 140 that generates a delay period clock, and an output clock changeover circuit 160 that selects the delay clock or the delay period clock, on the basis of the state of the synchronization pulse, and the synchronization clock generating circuits are connected in sequence in the order of greater delay time of the delay circuits, provided respectively to the synchronization clock generating circuits and having different delay times.
申请公布号 JP2003023417(A) 申请公布日期 2003.01.24
申请号 JP20010209392 申请日期 2001.07.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 EZAKI KOUTARO
分类号 H04L7/02 主分类号 H04L7/02
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