| 摘要 |
Frequency offset obtained by a frequency offset detecting circuit 2051 is output to a per-slot phase rotation correcting circuit 207 and per-symbol phase rotation correcting circuits 209 and 210. A maximum Doppler frequency (fD) obtained by an fD detecting circuit 2052 is output to a weight factor calculating circuit 208. The per-symbol phase rotation correcting circuits 209 and 210 calculate a phase rotation correction value DELTAthetasymbol of each symbol based on an amount of phase rotation of a frequency offset and outputs the value to multipliers 206 and 201. The per-slot phase rotation correcting circuit 207 calculates a phase rotation correction value DELTAthetaslot of each slot based on the amount of phase rotation of the frequency offset and outputs the value to a weighted adding circuit 204. In the weight factor calculating circuit 208, a weight factor (alpha) is calculated according to the detected fD value and is output to the weighted adding circuit 204.
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