| 摘要 |
<p>When a decoding circuit ( 22 a) decodes an instruction code stored in a pipeline register ( 21 d), the decoding circuit ( 22 a) decodes the device address. Based on this, it is decided which one of the device information of a RAM ( 11 ) and a RAM ( 12 ) is to be used. When the area of the RAM ( 12 ) has been assigned, the decoding circuit ( 22 a) outputs a signal showing that the number of stop of pipeline processing is 0, unlike the assignment of the RAM ( 11 ). Therefore, a pipeline register section ( 21 ) does not set the pipeline stop signal to 1. Consequently, the reading of the instruction code from the RAM ( 11 ) and the pipeline processing are not interrupted. As a result, it is possible to realize a structure in which execution of a high-speed processing is possible and a compact/low-cost structure in the same hardware.</p> |
