| 摘要 |
<p>An integrated circuit device having a first memory to/from which data can be input and/or output from/to a second memory and a processing unit capable of modifying a data flow at least partially. In the processing unit, there are provided a data processing section for processing data input and/or output from/to the first memory, a first address output section for outputting a first address of the data input and/or output between the first memory and the data processing section, and a second address output section for outputting a second address of the data input and/or output between the second memory and the first memory. By modifying a data flow or constituting a circuit for controlling a memory by a part of the reconfigurable processing unit, it is possible to constitute a cache memory system on an integrated circuit device optimal for processing executed on the integrated circuit device.</p> |
