发明名称 Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium
摘要 In a semiconductor device having a multiple layer wiring structure, a wiring method, a wiring device, and a recording medium, by optimizing the placement of SVIA, it is possible, for an intersection portion where a lower metal wiring layer having a width W1 and an upper metal wiring layer having a width W4 intersect with the intermediate metal layers sandwiched in between, to delete one row in the X direction and two rows in the Y direction for a total of nine SVIAs, when five SVIAs are arranged at the pitch PX in the X direction (i.e. in the transverse direction of the upper metal wiring layer) and three SVIAs are arranged at the pitch PY in the Y direction (i.e. in the transverse direction of the lower metal wiring layer) for a total of fifteen SVIAS. As a result, it is possible to secure one wiring track through which wiring is able to pass from among the three wiring tracks in the X direction and two wiring tracks through which wiring is able to pass from among the five wiring tracks in the Y direction.
申请公布号 US2003015800(A1) 申请公布日期 2003.01.23
申请号 US20020246633 申请日期 2002.09.19
申请人 FUJITSU LIMITED 发明人 FUKASAWA SHINJI
分类号 H01L21/3205;H01L21/768;H01L21/82;H01L21/822;H01L23/52;H01L23/528;H01L27/04;(IPC1-7):H01L23/48 主分类号 H01L21/3205
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