| 摘要 |
PURPOSE: A high-speed semiconductor memory device is provided to cancel an error caused when measuring core characteristic parameters by removing a delay difference between different core control signals during a test mode of operation. CONSTITUTION: A high-speed data transfer path comprises pads(140a,140b), switches(160a,160b), flip-flops(180a,180b), and buffers(200a,200b). The switches(160a,160b) are turned on in response to a test mode signal(TestMode) of a low level. The flip-flops(180a,180b) are disabled by the test mode signal(TestMode) of a high level, and operate in synchronization with a clock signal(CLK_HF) of a high operating frequency through corresponding AND gates(220a,220b). A test data transfer path is provided to transfer data from the pads(140a,140b) to a core peripheral circuit(120) during a test mode of operation. The test data transfer path comprises two switches(240a,240b), two flip-flops(260a,260b), and an AND gate(280). The flip-flop(260a) latches an external control signal transferred via the switch(240a) in synchronization with an output signal(ICLK_TEST) of the AND gate(280). The latched signal is provided to the buffer(200a). The flip-flop(260b) latches an external control signal transferred via the switch(240b) in synchronization with an output signal(ICLK_TEST) of the AND gate(280). The latched signal is provided to the buffer(200b). The AND gate(280) blocks a test clock signal(CLK_TEST) so as not to be transferred to the flip-flops(260a,260b), during a normal mode of operation.
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