发明名称 PROCESSOR HAVING REPLAY ARCHITECTURE WITH FAST AND SLOW REPLAY PATHS
摘要 According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
申请公布号 KR20030007425(A) 申请公布日期 2003.01.23
申请号 KR20027010573 申请日期 2000.12.29
申请人 发明人
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
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