| 摘要 |
The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a stage before a parallel-serial conversion circuit on the transmission side and an NRZI decoder and a bit unstuffing circuit are provided in a stage after a serial-parallel conversion circuit on the reception side, so that bit stuffing, NRZI encoding, NRZI decoding, and bit unstuffing are implemented on parallel data, not serial data. Any bits that have overflowed due to the bit insertion are carried forward to data for the next clock cycle and any deficiency of bits caused by bit deletion is moved up from the data of the next clock cycle. Insertion (or deletion) of bits is based on the thus calculated bit stuffing (or bit unstuffing) position and the range of parallel data to be output is based on the accumulated total of the number of bits that overflow (or contract).
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