| 摘要 |
PURPOSE: A method and an apparatus for matching data between devices having inter-different bus widths are provided to perform a data width conversion although an error is generated in a phase or frequency of a used clock signal by storing data in which a data widths is changed in FIFOs and outputting the data to the outside. CONSTITUTION: A plurality of FIFOs(410) synchronize data received from a device A(40) to an input clock signal, distributively store the data, and generate a frequency division circuit control signal. A frequency division circuit unit(510) generates a FIFO output clock signal according to the frequency division control signal for controlling the output of the data stored in the FIFOs(410), and transmits the FIFO output clock signal to the FIFOs(410). A multiplexer control unit(520) receives the FIFO output clock signal and generates a multiplexer output selecting signal. A multiplexer(420) multiplexes the data outputted from the FIFOs(410) according to the multiplexer output selecting signal, and successively outputs the data.
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