| 摘要 |
PURPOSE: A semiconductor integrated circuit is provided to be capable of testing each embedded TAP'ed core both at a chip state and at a board state. CONSTITUTION: TAP'ed cores(31,33) share four input pins(TDI,TMS,TRST,TCK). The input pin(TDI) is a serial test data input pin, the pin(TMS) is a test mode select signal input pin, the pin(TRST) is a test reset signal input pin, the pin(TCK) is a test clock signal input pin, and the pin(TDO) is a test data output pin. A boundary scan register circuit(37) has an input terminal connected to the data input pin(TDI). A select signal generating circuit(39) has input terminals connected to the pins(TDI,TRST,TCK), and generates select signals(SE0,SE1) for selecting one of the TAP'ed cores(31,33) and the boundary scan register circuit(37) in response to signals received via the input terminals of the circuit(39). A selector(35) selects one of outputs of the cores(31,33) and an output of the boundary scan register circuit(37) in response to the select signals(SE0,SE1).
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