| 摘要 |
A semiconductor memory is disclosed, the memory comprising memory cells each comprising a transistor having a control gate and a floating gate. During a period in which data write to a memory cell is performed, a positive voltage (a voltage substantially 1/2 the power supply voltage or more, and lower than the power supply voltage) is supplied to a memory cell source line (ARVSS) for supplying a reference potential to the memory cell. Even if a bit line (BL1-BL4) and the memory cell source line (ARVSS) are short-circuited, the potential of a node in a latch buffer unit is maintained at least during a period in which this node and the bit line are electrically connected. Since this makes it possible to determine that a program operation is normally performed and to complete a program verify operation, a defect caused by the short circuit between the bit line (BL1-BL4) and the memory cell source line (ARVSS) can be repaired by using a redundancy circuit. <IMAGE>
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