发明名称 |
Power down voltage control method and apparatus |
摘要 |
A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.
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申请公布号 |
US6510096(B2) |
申请公布日期 |
2003.01.21 |
申请号 |
US20010981945 |
申请日期 |
2001.10.17 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI JONG-HYUN;YOO JEI-HWAN;LEE JONG-EON;JANG HYUN-SOON |
分类号 |
G11C11/407;G11C5/14;G11C7/22;(IPC1-7):G11C8/02 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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