发明名称 |
Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports |
摘要 |
An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.
|
申请公布号 |
US6510483(B1) |
申请公布日期 |
2003.01.21 |
申请号 |
US20000531365 |
申请日期 |
2000.03.21 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
REZEANU STEFAN-CRISTIAN;ALLAN JAMES;HAMADEH EMAD;GROSS ERIC;SRINIVASARAGHAVAN VIJAY;MANNING ROBERT |
分类号 |
G11C7/10;(IPC1-7):G06F13/40;G06F3/00;G06F1/04;G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|