发明名称 |
Method for using a recovered data-encoded clock to convert high-frequency serial data to lower frequency parallel data |
摘要 |
An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.
|
申请公布号 |
US6509851(B1) |
申请公布日期 |
2003.01.21 |
申请号 |
US20000538201 |
申请日期 |
2000.03.30 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
CLARK LEAH S.;LARKY STEVEN P. |
分类号 |
H03M9/00;(IPC1-7):H03M9/00 |
主分类号 |
H03M9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|