发明名称 |
Clock signal generator/converter device |
摘要 |
The device converts a clock signal into a second clock signal having a different clock rate. This allows converting a first data signal into a second data signal having an altered data rate. Controlling the frequency dividers particularly in the feedback path of the phase-locked loops enables matching to the different data rates and conversion between both data signals DS1 into DS2, or DS2 into DS1.
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申请公布号 |
US6509769(B2) |
申请公布日期 |
2003.01.21 |
申请号 |
US20000734463 |
申请日期 |
2000.12.11 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
DAUTH FRITZ-JOERG |
分类号 |
H03L7/23;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/23 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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