Method for forming high performance CMOS devices with elevated sidewall spacers

摘要

A method is described for making elevated sidewall spacers on the gate structure of a semiconductor device. A first insulating layer is deposited on the substrate, so that an upper portion of each of the sidewalls extends above the layer. A second insulating layer is deposited on the first layer and on the gate structure. Portions of the second layer disposed on the first layer and on the top surface of the gate structure are removed, so that a remaining portion of the second layer is disposed on the upper portion of each of the sidewalls. The first layer is then removed, so that the remaining portion of the second layer on each of the sidewalls projects laterally therefrom and is elevated with respect to the substrate. This structure is used to implant PFET and NFET extension regions without dose loss.