| 摘要 |
A write register access circuit 201 comprises data input terminals 1e01~1e32, 32 pieces of first-stage flip-flops 1a01~1a32, 16 pieces of second-stage flip-flops 1b01~1b16 connected to the first-stage flip-flops 1a01~1a16, an OR gate 1g, a flip-flop 1h, a NAND gate 11, 16 pieces of data selector circuits 1c01~1c16, 32 pieces of gate circuits 1d01~1d32, and 32 pieces of data output terminals 1f01~1f32, and the write register access circuit 201 is connected to a CPU circuit 215 through an interruption request circuit Z. Therefore, when the write register access circuit 201 is included in an LSI, the write register access circuit 201 enables parallel processing between the CPU and the LSI without necessity of matching the instruction word length of the CPU and the bus width of the LSI, providing an internal bus width changing switch, and dealing with the problem at the software end of the CPU. Further, data transfer rate is increased.
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