Robust shadow bitline circuit technique for high-performance register files

摘要

A method and apparatus to improve register file performance. In various embodiments, a shadow bitline runs parallel to a local bitline in a register file, and the shadow bitline is coupled to a subset of the data cells to which the local bitline is coupled. In operation, a static keeper holds the local bitline in a condition complementary to the condition of the shadow bitline, when appropriate.