发明名称 METHOD FOR REDUCING QUANTITY OF INTER-PROCESSOR COMMUNICATION, PARALLEL COMPILER DEVICE AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a system capable of reducing the quantity of inter-processor communication at the time of executing a program in a parallel compiler. SOLUTION: An optimizing part 34 in the parallel compiler 3 is provided with an array selection means 342 for registering arrays in a suitable part of an information table by selecting arrays included in a sentence in a loop to be processed which is judged as the possibility of parallel processing, preparing an information table concerned with the arrays included in the loop from the shapes of the arrays, the formats of subscripts of the arrays and a distributed state to distributed memories, checking whether a template matched with the arrays exists or not, preparing a template of block constitution defined in accordance with the shapes of the arrays and the formats of subscripts when the template matched with the arrays does not exist, and aligning the arrays to the template matched with the arrays and a processor selection means 341 for calculating the quantity of communication in each divided block of the information table when the arrays included in the sentence in the loop to be processed are registered and determining a calculation execution processor from the quantity of communication of the information table.
申请公布号 JP2003015883(A) 申请公布日期 2003.01.17
申请号 JP20010199321 申请日期 2001.06.29
申请人 NEC CORP 发明人 SAKATA DAISUKE
分类号 G06F15/16;G06F9/45;G06F15/177;(IPC1-7):G06F9/45 主分类号 G06F15/16
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