| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same for reducing parasitic resistance, and thereby monitoring transistor properties easily and at an early stage of wafer process. SOLUTION: Lead wiring layers 11a and 11c are electrically connected to each pair of source/drain region 3 of a monitor transistor MT. These lead wiring layers 11a and 11c are formed on an insulation layer 10, which is same with the insulation layer where a conducting layer for a bit line of memory cell region is formed. Each of the lead wiring layers 11a and 11c has contact units 11b and 11d which are wide enough to connect a probe needle thereto from outside. |
