| 摘要 |
PROBLEM TO BE SOLVED: To provide a cell arrangement method for a semiconductor integrated circuit, that can shorten delay and wire length by reducing the number of critical nets. SOLUTION: A logic file and a library are inputted first of all, and cells, in which the number of terminals constituting a net and the number of input/ output terminals of cells constituting the net are two respectively, and the total of the widths of the cells constituting the net is not longer than a given, are extracted as a cell group candidate (301 and 302). In the case there are candidate cells, cell groups for cell grouping candidates are ranked with the driving performance rates of the cells that are a candidate, the number of input/output terminals to be reduced by grouping and the number of pins for the cells to be grouped as evaluation values (303 and 304). Then, grouping processing is applied to grouping candidate cell groups in accordance with the obtained ranking to return to processing from the step 302 (305). When all the candidate cells are processed and no candidate cell retains in check of the step 303, a grouped cell is handled in the same manner as that of a normal cell to be subjected to arrangement processing (306).
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