| 摘要 |
<p>PROBLEM TO BE SOLVED: To achieve a high speed operation by pre-charging and equalizing bit lines at high speed while suppressing the scale of an internal voltage drop circuit. SOLUTION: In a pair of complementary type bit lines BL1/BL1# connected to a selected memory cell 3a, pre-charging and equalization are performed by supplying electric power from two systems of an internal voltage drop circuit 11 and a Vcc pre-charge circuit 12. Therefore, a load to be driven by the internal voltage drop circuit 11 is by far lighter than that in conventional technology and a small capacitor can be used, and hence the chip area occupied by the internal voltage drop circuit 11 is significantly reduced. Also, operation speed is increased compared wit the case in which pre-charge and equalization are performed with only one system in the internal voltage drop circuit 11 of conventional technology.</p> |
