发明名称 MASK BLOCK MANUFACTURING METHOD, MASK CLOCK, AND ALIGNER
摘要 <p>PROBLEM TO BE SOLVED: To improve the throughput of a process for exposing a semiconductor device having a plurality of layers. SOLUTION: Through steps S20 to S22, blocks including basic figures included in respective layers of IC data 40 are extracted respectively. For example, blocks are extracted from a wiring layer in the step S20, from a gate layer in the step S21, and from a Hall layer in the step S22. When the blocks extracted in the steps S20 to S22 are more than blocks which can be arranged on a block mask, the blocks are selected, for example, in the decreasing order their use frequencies in a step S23. In a step S24, the arrangement of the blocks selected in the step S23 is so determined that a block is closer and closer to the center of the block mask as the size of the minimum exposure pattern included in the block is smaller and smaller. Data having the arrangement determined are outputted as data 41 for block mask formation.</p>
申请公布号 JP2003017388(A) 申请公布日期 2003.01.17
申请号 JP20010199180 申请日期 2001.06.29
申请人 FUJITSU LTD 发明人 TAKITA HIROSHI;HOSHINO HIROMI
分类号 G03F1/20;G03F1/68;H01J37/302;H01L21/027;(IPC1-7):H01L21/027;G03F1/16 主分类号 G03F1/20
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