发明名称 ERROR CORRECTION CIRCUIT AND ERROR CORRECTION METHOD
摘要 PROBLEM TO BE SOLVED: To provide an error correction circuit and an error correction method, that can use a trellis decoder in n kinds of states, that is, a trellis decoder capable of conducting decoding in a plurality of different kinds of states, so as to decode data without producing coset. SOLUTION: A branch metric production circuit 201 generates each branch metric, with respect to each code data. An ACS circuit 202 sums each range metric and a path metric in each state, compares the sums, and selects the smallest sum for a new path metric in each state and stores data, corresponding to the selected path in each state to a path memory. A trace back processing circuit 204 traces back a predetermined cut-off path length along a surviving path, which contains a state whose new path metric is smallest, so as to determine data Y2 Y1 (4-states) or data X2 X1 (8-states). Using the configuration above, decoder can decode data using one 4-state and 8-state which are common use trellis.
申请公布号 JP2003018018(A) 申请公布日期 2003.01.17
申请号 JP20020127515 申请日期 2002.04.26
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KISODA AKIRA;SENDA HIROYUKI;KAMATA TAKEHIRO
分类号 G06F11/10;H03M13/25;H04L1/00;H04L27/02;(IPC1-7):H03M13/25 主分类号 G06F11/10
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