发明名称 DATA WRITE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a data write circuit that permits byte access with a 32-bit CPU. SOLUTION: The CPU 11, when it executes byte writing, outputs 0 as data DS. One of AND gates 23 to 26 is selected with the data DS and lower two bits of a CPU address, and the output turns to 1. To the first and second input ends of selectors 35 to 38, the output data of a memory 13 and the output data of the CPU 11 are impressed, respectively. Then, for instance, if the output of the AND gate 26 becomes 1, the output data of the CPU 11 is outputted from the selector 38, and the output data of the memory 13 is outputted from other selectors 35 to 37. Thereby, only the 0th to the seventh bit of the output data of the memory 13 are rewritten into CPU data, which are written into the memory 13.
申请公布号 JP2003015952(A) 申请公布日期 2003.01.17
申请号 JP20010201254 申请日期 2001.07.02
申请人 YAMAHA CORP 发明人 ANDO TOMOAKI
分类号 G06F12/06;G06F12/04;G11C7/10;G11C11/4093;(IPC1-7):G06F12/06 主分类号 G06F12/06
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