发明名称 CLOCK REGENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a clock regenerating circuit which quickly leads in a clock again even in a communication line where blocking of mobile communication or the like frequently occurs. SOLUTION: A typical clock regenerating circuit including a phase comparator 14, a loop filter 15, and a VCO 18 is provided with a loop filter output holder 13 provided with a memory 43, and an adder 17. When a reception signal is restored after the occurrence of blocking, the output value of the loop filter 15 just before the occurrence of blocking is read out from the loop filter output holder 13 and is added to the output of the loop filter 15 by the adder 17, and the VCO 18 is controlled by the value obtained by this addition to quickly lead in the clock.
申请公布号 JP2003018229(A) 申请公布日期 2003.01.17
申请号 JP20010202120 申请日期 2001.07.03
申请人 NEC ENG LTD 发明人 KAKIHARA SHIYOUJI
分类号 H03L7/093;H03L7/10;H04L27/22 主分类号 H03L7/093
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