| 摘要 |
<p>A processor cluster according to the invention is implemented on a single integrated circuit comprising a configurable cache memory (1) and a plurality of processors (2a,...,2e). At least two processors (2a, 2b) have mutually different instruction sets. The processor cluster further comprises a selection unit (6) for selectively activating one of the plurality of processors and giving said selected processor access to the cache memory.</p> |
