发明名称 Passivation and planarization process for flip chip packages
摘要 A method including the step of forming contact pads on a semiconductor wafer. A passivation blanket is deposited over the semiconductor wafer and the contact pads. The passivation blanket includes three layers. A first layer of silicon dioxide is deposited over the semiconductor wafer and the contact pads. A second layer of silicon nitride is deposited over the first layer, and a third layer and final layer of silicon dioxide is deposited over the second layer. The passivated semiconductor wafer is planarized using an oxide chemical mechanical planarization method. Holes are opened in the passivation blanket down to the contact pads. An under bump metallurgy is deposited onto the contact pads and a portion of the final silicon dioxide layer. Solder is deposited onto the under bump metallurgy and reflown to form a flip chip having solder bumps.
申请公布号 US2003013291(A1) 申请公布日期 2003.01.16
申请号 US20010904363 申请日期 2001.07.12
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHEN DIAN-HAU;WU LIN-JUNE;LIN KWANG-MING
分类号 H01L21/60;H01L23/485;(IPC1-7):H01L21/44 主分类号 H01L21/60
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