| 摘要 |
A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to various metal layers in the IC core. Digital, analog, and memory power zones indicating the power consumption of regions within the core and are also mapped to the core. An equivalent circuit of the floor plan, including a resistor array and current sources is generated in a netlist. The netlist is simulated, with the current density and voltage drop of power-bus wire segments calculated. Calculated current density and voltage drop values are analyzed in the floor plan design using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration or voltage drop problems. The designer can modify the floor plan design quickly and easily if the calculated current density and voltage drop values indicate potential electromigration or voltage drop problems.
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