发明名称 SEMICONDUCTOR MEMORY WITH IMPROVED SOFT ERROR RESISTANCE
摘要 A semiconductor memory includes a first inverter, a second inverter and a read circuit. The first inverter has its input terminal connected to a first memory node and its output terminal connected to a second memory node. The second inverter is connected in anti-parallel with the first inverter, that is, has its input terminal connected to the second memory node and its output terminal connected to the first memory node. The read circuit includes a first transistor having its gate connected to the first memory node, a second transistor having its gate connected to the second memory node, and a third transistor for connecting the drain of the first transistor and that of the second transistor to a read bit line. The semiconductor memory can improve its soft error resistance without increasing the number of steps of the manufacturing process.
申请公布号 US2003012074(A1) 申请公布日期 2003.01.16
申请号 US20020141184 申请日期 2002.05.09
申请人 NII KOJI;OKUDA SHOJI 发明人 NII KOJI;OKUDA SHOJI
分类号 G11C11/41;G11C7/02;G11C8/16;G11C11/412;G11C11/419;(IPC1-7):G11C7/00 主分类号 G11C11/41
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